Typical commercial semiconductor devices are formed from silicon. In these devices, regions of the silicon are doped with impurities to vary the conductivity and form junctions, which can be used to form, for example, transistors. In most commercially available devices, these transistor devices are formed in a semiconductor substrate. For example, the devices may be formed within a lightly doped well within a monocrystalline silicon substrate. In other devices, known as silicon-on-insulator (SOI), a silicon layer is formed over an insulating layer, which is formed on the substrate. Transistor devices can then be formed in the upper silicon layer.
Enhanced electron mobility in silicon under tensile channel strain and enhanced hole mobility in silicon-germanium (SiGe) under compressive channel strain have been reported. See e.g., Ismail et al., “Electron transport properties of Si/SiGe heterostructures: Measurements and device implications,” Applied Physics Letters Vol. 63, No. 5, 2, Aug. 1993, pp. 660-662; and Nayak et al., “Enhancement-Mode Quantum-Well GexSi1−x PMOS,” IEEE Electron Device Letters, Vol. 12, No. 4, April 1991, pp. 154-156. Both of these papers are incorporated herein by reference.
Recent studies have shown the feasibility of strained Si/SiGe-on-Insulator (SiGe-OI) structure. For example, Gamiz et al. have shown by Monte Carlo simulation that electron mobility is greater when strained-silicon inversion layers are grown on SiGe-on-insulator substrates than when unstrained-silicon-on-insulator devices are employed. Gamiz et al., “Strained-Si/SiGe-on-insulator inversion layers: The role of strained-Si layer thickness on electron mobility,” Applied Physics Letters, vol. 80, no. 22, 3, Jun. 2002, pp. 4160-62; see also Gamiz et al., “Electron Transport in strained Si inversion layers grown on SiGe-on-insulator substrates,” Journal of Applied Physics, vol. 92, no. 1, 1, Jul. 2002, pp. 288-295. Both of these papers are incorporated herein by reference.
Mizuno et al. have studied p-channel advanced SOI MOSFETs using double SiGe heterostructures fabricated by the combination of SIMOX and high-quality strained-Si/SiGe regrowth technologies, in order to introduce higher strain in the silicon channel. Mizuno et al., “Novel SOI p-Channel MOSFETs With Higher Strain in Si Channel Using Double SiGe Heterostructures,” IEEE Transactions on Electron Devices, vol. 49, no. 1, January 2002, pp. 7-14; see also Tezuka et al., “High-performance Strained Si-on-Insulator MOSFETs by Novel Fabrication Processes Utilizing Ge-Condensation Technique,” 2002 Symposium on VLSI Technology Digest of Technical Papers, pp. 97-97. Both of these papers are incorporated herein by reference.